109 search results - page 18 / 22 » Crosstalk noise in FPGAs |
TSP
2010
13 years 2 months ago
2010
[1, 2] have shown for the dynamic spectrum allocation problem that a competitive market model (which sets a price for transmission power on each channel) leads to a greater social...
IOLTS
2003
IEEE
14 years 27 days ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...