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CODES
2001
IEEE
13 years 11 months ago
Development cost and size estimation starting from high-level specifications
This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modificatio...
William Fornaciari, Fabio Salice, Umberto Bondi, E...
TVLSI
2010
13 years 2 months ago
Asynchronous Data-Driven Circuit Synthesis
A method is described for synthesizing asynchronous circuits based on the Handshake Circuit paradigm but employing a data-driven, rather than a control-driven, style. This approach...
Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A...
ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
14 years 2 months ago
CMOS Control Enabled Single-Type FET NASIC
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
Pritish Narayanan, Michael Leuchtenburg, Teng Wang...
ISLPED
2010
ACM
158views Hardware» more  ISLPED 2010»
13 years 8 months ago
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both...
Weixun Wang, Xiaoke Qin, Prabhat Mishra
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
14 years 4 days ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel