Sciweavers

508 search results - page 50 / 102
» DNS performance and the effectiveness of caching
Sort
View
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
14 years 29 days ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
ISCA
2003
IEEE
93views Hardware» more  ISCA 2003»
14 years 29 days ago
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
Ravi Bhargava, Lizy Kurian John
CEE
2008
119views more  CEE 2008»
13 years 7 months ago
A clustering-based prefetching scheme on a Web cache environment
Web prefetching is an attractive solution to reduce the network resources consumed by Web services as well as the access latencies perceived by Web users. Unlike Web caching, whic...
George Pallis, Athena Vakali, Jaroslav Pokorn&yacu...
ICCD
2006
IEEE
124views Hardware» more  ICCD 2006»
14 years 4 months ago
Customizable Fault Tolerant Caches for Embedded Processors
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
14 years 4 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...