103 search results - page 18 / 21 » DPA Leakage Models for CMOS Logic Circuits |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
MICRO
2006
IEEE
13 years 7 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...