103 search results - page 5 / 21 » DPA Leakage Models for CMOS Logic Circuits |
CHES
2006
Springer
13 years 11 months ago
2006
Springer
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
PATMOS
2004
Springer
14 years 26 days ago
2004
Springer
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
Abstract— This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have uniqu...
ISLPED
2000
ACM
13 years 12 months ago
2000
ACM
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelect...