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» Data Dependent Power Use in Multipliers
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GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 19 days ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
14 years 7 months ago
Designing Leakage Aware Multipliers
Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. ...
M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishn...
VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
14 years 7 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
ARITH
2007
IEEE
14 years 1 months ago
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
Libo Huang, Li Shen, Kui Dai, Zhiying Wang
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 18 days ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...