1602 search results - page 124 / 321 » Database Architectures for New Hardware |
HPN
1992
13 years 11 months ago
1992
This paper describes a new host interface architecture for high-speed networks operating at 800 of Mbit/second or higher rates. The architecture is targeted to achieve several 100...
ICCAD
2009
IEEE
13 years 8 months ago
2009
IEEE
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
SIGOPS
2011
13 years 5 months ago
2011
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
IEEEPACT
2007
IEEE
14 years 4 months ago
2007
IEEE
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...
ICCD
2004
IEEE
14 years 7 months ago
2004
IEEE
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...