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ISCAS
1994
IEEE
117views Hardware» more  ISCAS 1994»
14 years 27 days ago
Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy
This paper presents a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both sorting and p...
Wen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
14 years 24 days ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
FPL
2007
Springer
97views Hardware» more  FPL 2007»
14 years 20 days ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
CSB
2004
IEEE
108views Bioinformatics» more  CSB 2004»
14 years 16 days ago
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA
Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
Terrence S. T. Mak, Kai-Pui Lam
ASPDAC
2000
ACM
109views Hardware» more  ASPDAC 2000»
14 years 12 days ago
A technique for QoS-based system partitioning
Quality of service (QoS) has been an important topic of many research communities. Combined with an advanced and retargetable compiler, variability of applicationsspecific very lar...
Johnson S. Kin, Chunho Lee, William H. Mangione-Sm...