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IEEEPACT
2005
IEEE
14 years 2 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
SENSYS
2005
ACM
14 years 2 months ago
Cyclops: in situ image sensing and interpretation in wireless sensor networks
Despite their increasing sophistication, wireless sensor networks still do not exploit the most powerful of the human senses: vision. Indeed, vision provides humans with unmatched...
Mohammad H. Rahimi, Rick Baer, Obimdinachi I. Iroe...
ITC
2003
IEEE
136views Hardware» more  ITC 2003»
14 years 2 months ago
Adapting JTAG for AC Interconnect Testing
The use of AC coupled interconnects to provide communication paths between devices is increasing. The existing IEEE 1149.1 boundary scan standard [1] (JTAG) has limitations that h...
Lee Whetsel
HIPC
1999
Springer
14 years 1 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
FCCM
1998
IEEE
149views VLSI» more  FCCM 1998»
14 years 1 months ago
Configuration Compression for the Xilinx XC6200 FPGA
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
Scott Hauck, Zhiyuan Li, Eric J. Schwabe