165 search results - page 4 / 33 » Dataflow Architectures for GALS |
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Due to increasing clock speeds and shrinking technologies, distributing a single global clock signal throughout a chip is becoming a difficult and challenging proposition. In this...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This paper presents efficient automatic code synthesis techniques from dataflow graphs for multimedia applications. Since multimedia applications require large size buffers contai...
NOCS
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
ICDE
2003
IEEE
14 years 10 months ago
2003
IEEE
The long-running nature of continuous queries poses new scalability challenges for dataflow processing. CQ systems execute pipelined dataflows that may be shared across multiple q...