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ICCD
1992
IEEE
126views Hardware» more  ICCD 1992»
14 years 20 days ago
High-Level State Machine Specification and Synthesis
Current synthesis methodologies based on hardwaredescription languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
ISSS
1995
IEEE
121views Hardware» more  ISSS 1995»
14 years 4 days ago
A comprehensive estimation technique for high-level synthesis
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...
Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min X...
VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
14 years 25 days ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
14 years 1 months ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
DATE
2010
IEEE
193views Hardware» more  DATE 2010»
14 years 1 months ago
Coordinated resource optimization in behavioral synthesis
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
Jason Cong, Bin Liu, Junjuan Xu