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125
Voted
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error dete...
118
Voted
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...
112
click to vote
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophistic...
81
Voted
DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimati...
93
Voted
DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...