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2000
IEEE
85views Hardware» more  DATE 2000»
15 years 8 months ago
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses
This paper proposes an all digital on-chip bus delay and crosstalk measurement methodology. A diagnosis procedure is derived to distinguish the delay faults in drivers, receivers,...
Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Na...
151
Voted
DATE
1999
IEEE
64views Hardware» more  DATE 1999»
15 years 8 months ago
Dynamic Power Management for non-stationary service requests
Dynamic Power Management is a design methodology aiming at reducing power consumption of electronic systems, by performing selective shutdown of the idle system resources. The eff...
Eui-Young Chung, Luca Benini, Alessandro Bogliolo,...
129
Voted
DATE
1999
IEEE
113views Hardware» more  DATE 1999»
15 years 8 months ago
Cycle-based Simulation with Decision Diagrams
This paper addresses the problem of efficient functional simulation of synchronous digital systems. A technique based on the use of Decision Diagrams (DD) for representing the fun...
Raimund Ubar, Jaan Raik, Adam Morawiec
128
Voted
DATE
1998
IEEE
109views Hardware» more  DATE 1998»
15 years 8 months ago
Cross-Level Hierarchical High-Level Synthesis
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
Oliver Bringmann, Wolfgang Rosenstiel
101
Voted
DATE
1997
IEEE
86views Hardware» more  DATE 1997»
15 years 7 months ago
Highly scalable parallel parametrizable architecture of the motion estimator
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for di eren...
Radim Cmar, Serge Vernalde