Sciweavers

1581 search results - page 164 / 317
» Date Warehouse Design
Sort
View
DATE
1999
IEEE
80views Hardware» more  DATE 1999»
15 years 8 months ago
Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares
Reachability analysis of finite state machines is essential to many computer-aided design applications. We present new techniques to improve both approximate and exact reachabilit...
Youpyo Hong, Peter A. Beerel
DATE
1999
IEEE
72views Hardware» more  DATE 1999»
15 years 8 months ago
On Programmable Memory Built-In Self Test Architectures
The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more e ci...
Kamran Zarrineh, Shambhu J. Upadhyaya
DATE
1998
IEEE
76views Hardware» more  DATE 1998»
15 years 8 months ago
Gated Clock Routing Minimizing the Switched Capacitance
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
Jaewon Oh, Massoud Pedram
DATE
1997
IEEE
92views Hardware» more  DATE 1997»
15 years 8 months ago
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits
The paper proposes a novel approach in an attempt to solve the test problem for sequential circuits. Up until now, most of the classical test pattern techniques use a number of al...
A. Dargelas, C. Gauthron, Yves Bertrand
DATE
2009
IEEE
64views Hardware» more  DATE 2009»
15 years 7 months ago
Speculative reduction-based scalable redundancy identification
The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inhere...
Hari Mony, Jason Baumgartner, Alan Mishchenko, Rob...