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DATE
2005
IEEE
111views Hardware» more  DATE 2005»
15 years 6 months ago
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 4 months ago
Automatic pipelining from transactional datapath specifications
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-...
DATE
2010
IEEE
139views Hardware» more  DATE 2010»
15 years 20 days ago
A general mathematical model of probabilistic ripple-carry adders
Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible ...
Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Aru...
COMSUR
2011
213views Hardware» more  COMSUR 2011»
14 years 3 months ago
Securing BGP - A Literature Survey
Abstract—The Border Gateway Protocol (BGP) is the Internet’s inter-domain routing protocol. One of the major concerns related to BGP is its lack of effective security measures,...
Geoff Huston, Mattia Rossi, Grenville J. Armitage
DATE
2009
IEEE
125views Hardware» more  DATE 2009»
15 years 10 months ago
HLS-l: High-level synthesis of high performance latch-based circuits
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
Seungwhun Paik, Insup Shin, Youngsoo Shin