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DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 2 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
DATE
2005
IEEE
104views Hardware» more  DATE 2005»
14 years 2 months ago
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC
In this paper, we present a SoC design methodology joining the capabilities of UML and SystemC to operate at systemlevel. We present a UML 2.0 profile of the SystemC language expl...
Elvinia Riccobene, Patrizia Scandurra, Alberto Ros...
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
14 years 2 months ago
Design Method for Constant Power Consumption of Differential Logic Circuits
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the en...
Kris Tiri, Ingrid Verbauwhede
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
14 years 1 months ago
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
Michael Pronath, Helmut E. Graeb, Kurt Antreich