48 search results - page 5 / 10 » Defect tolerance for nanocomputer architecture |
IOLTS
2008
IEEE
14 years 2 months ago
2008
IEEE
With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this pr...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract— Physics offers several active devices with nanometerscale footprint, which can be best used in combination with a CMOS subsystem. Such hybrid circuits offer the potenti...