27 search results - page 4 / 6 » Delay Minimal Decomposition of Multiplexers in Technology Ma... |
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
TCAD
1998
13 years 7 months ago
1998
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
TC
2008
13 years 7 months ago
2008
Next-generation scientific applications require the capability to visualize large archival data sets or on-going computer simulations of physical and other phenomena over wide-area...