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» Delay modelling improvement for low voltage applications
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ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
14 years 1 months ago
A low-power clock frequency multiplier
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...
Md. Ibrahim Faisal, Magdy A. Bayoumi, Peiyi Zhao
WCNC
2008
IEEE
14 years 2 months ago
Novel Ultra Wideband Low Complexity Ranging Using Different Channel Statistics
—UWB technology can reach centimetre level ranging and positioning accuracy in LOS propagation when time of arrival techniques are used. However, in a real positioning system, th...
Giovanni Bellusci, Gerard J. M. Janssen, Junlin Ya...
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
14 years 17 hour ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
CDC
2010
IEEE
167views Control Systems» more  CDC 2010»
13 years 2 months ago
Numerical methods for the optimization of nonlinear stochastic delay systems, and an application to internet regulation
The Markov chain approximation method is an effective and widely used approach for computing optimal values and controls for stochastic systems. It was extended to nonlinear (and p...
Harold J. Kushner
DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy