424 search results - page 7 / 85 » Delay modelling improvement for low voltage applications |
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
CCR
2006
13 years 8 months ago
2006
The delay and throughput characteristics of a packet switch depend mainly on the queueing scheme and the scheduling algorithm deployed at the switch. Early research on scheduling ...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
ISLPED
2010
ACM
13 years 8 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...