25 search results - page 4 / 5 » Delay variation tolerance for domino circuits |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
According to the current trend of increasing variations in process technologies and thus in performance, the conservative worst-case design will not work since design margins can ...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
—Increasing power density causes die overheating due to limited cooling capacity of the package. Conventional thermal management techniques e.g. logic shutdown, clock gating, fre...
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...