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VLSID
2002
IEEE
106views VLSI» more  VLSID 2002»
14 years 7 months ago
SWASAD: An ASIC Design for High Speed DNA Sequence Matching
This paper presents the Smith and Waterman Algorithm-Specific ASIC Design (SWASAD) project. This is a hardware solution that implements the S&W algorithm.. The SWASAD is an imp...
Tony Han, Sri Parameswaran
ISCAS
2005
IEEE
185views Hardware» more  ISCAS 2005»
14 years 9 days ago
2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...
Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu
ICCD
2003
IEEE
143views Hardware» more  ICCD 2003»
14 years 1 hour ago
Aggressive Test Power Reduction Through Test Stimuli Transformation
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
Ozgur Sinanoglu, Alex Orailoglu
ISQED
2000
IEEE
117views Hardware» more  ISQED 2000»
13 years 11 months ago
Realistic Worst-Case Modeling by Performance Level Principal Component Analysis
A new algorithm to determine the number and value of realistic worst-case models for the performance of module library components is presented in this paper. The proposed algorith...
Alessandra Nardi, Andrea Neviani, Carlo Guardiani
ICMI
2003
Springer
131views Biometrics» more  ICMI 2003»
13 years 12 months ago
A system for fast, full-text entry for small electronic devices
A novel text entry system designed based on the ubiquitous 12button telephone keypad and its adaptation for a soft keypad are presented. This system can be used to enter full text...
Saied Bozorgui-Nesbat