86 search results - page 15 / 18 » Delay-Reduced Combinational Logic Synthesis using Multiplexe... |
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
ASAP
2004
IEEE
14 years 9 days ago
2004
IEEE
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
TCAD
2002
13 years 8 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
GECCO
2005
Springer
2005
Springer
Providing information from the environment for growing electronic circuits through polymorphic gates
14 years 2 months ago
This paper deals with the evolutionary design of programs (constructors) that are able to create (n+2)-input circuits from n-input circuits. The growing circuits are composed of p...