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CODES
2003
IEEE
15 years 8 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
ASPDAC
2010
ACM
151views Hardware» more  ASPDAC 2010»
15 years 1 days ago
Source-level timing annotation for fast and accurate TLM computation model generation
This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling ...
Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay
122
Voted
DSD
2009
IEEE
93views Hardware» more  DSD 2009»
15 years 12 days ago
Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models
Several traditional VHDL fault injection mechanisms like mutants or saboteurs have been adapted to SystemC model descriptions. The main drawback of these approaches is the necessi...
Antonio da Silva, Sebastian Sanchez
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 8 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
162
Voted
DSRT
2008
IEEE
15 years 4 months ago
RTPROC: A System for Rapid Real-Time Prototyping in Audio Signal Processing
In this contribution a new system for the rapid development of real-time prototypes for digital audio signal processing algorithms on Windows PCs and a Digital Signal Processor (D...
Hauke Krüger, Peter Vary