123 search results - page 3 / 25 » Design For Testability Method for CML Digital Circuits |
DAC
1999
ACM
13 years 12 months ago
1999
ACM
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
ITC
2003
IEEE
14 years 28 days ago
2003
IEEE
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allow...
EH
2003
IEEE
14 years 29 days ago
2003
IEEE
The paper deals with a class of image filters in which the evolutionary approach consistently produces excellent and innovative results. Furthermore, a method is proposed that le...
ASYNC
1999
IEEE
13 years 12 months ago
1999
IEEE
Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facili...
DELTA
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string Digital/Analog converter(DAC). The results show that a...