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DATE
2010
IEEE
159views Hardware» more  DATE 2010»
14 years 25 days ago
A rapid prototyping system for error-resilient multi-processor systems-on-chip
—Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only...
Matthias May, Norbert Wehn, Abdelmajid Bouajila, J...
DAC
2002
ACM
14 years 8 months ago
A solenoidal basis method for efficient inductance extraction
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
Hemant Mahawar, Vivek Sarin, Weiping Shi
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 19 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
INFOCOM
1992
IEEE
13 years 11 months ago
Design of Virtual Channel Queue in an ATM Broadband Terminal Adaptor
In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect diffe...
H. Jonathan Chao, Donald E. Smith
PODC
1995
ACM
13 years 11 months ago
A Framework for Protocol Composition in Horus
The Horus system supports a communication architecture ats protocols as instances of an abstract data type. This approach encourages developers to partition complex protocols into...
Robbert van Renesse, Kenneth P. Birman, Roy Friedm...