In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
The continual shrinkage of minimum feature size in integrated circuit (IC) fabrication incurs more and more serious distortion in the optical lithography process, generating circu...
This paper concerns the study of the optimal performance computation of a semi-active suspension evaluated in terms of comfort and handling performances. To this aim the semi-activ...
Charles Poussot-Vassal, Sergio M. Savaresi, Cristi...
Abstract - In this paper, we propose the concept of System-InPackage (SIP) as a generalization of System-On-Chip (SOC). System-In-Package overcomes formidable integration barriers ...
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...