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» Design Methodology for Analog High Frequency ICs
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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
14 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
ICIP
2008
IEEE
14 years 9 months ago
Inverse image problem of designing phase shifting masks in optical lithography
The continual shrinkage of minimum feature size in integrated circuit (IC) fabrication incurs more and more serious distortion in the optical lithography process, generating circu...
Stanley H. Chan, Edmund Y. Lam
CDC
2010
IEEE
129views Control Systems» more  CDC 2010»
13 years 2 months ago
A methodology for optimal semi-active suspension systems performance evaluation
This paper concerns the study of the optimal performance computation of a semi-active suspension evaluated in terms of comfort and handling performances. To this aim the semi-activ...
Charles Poussot-Vassal, Sergio M. Savaresi, Cristi...
ASPDAC
2000
ACM
108views Hardware» more  ASPDAC 2000»
13 years 11 months ago
System-in-package (SIP): challenges and opportunities
Abstract - In this paper, we propose the concept of System-InPackage (SIP) as a generalization of System-On-Chip (SOC). System-In-Package overcomes formidable integration barriers ...
King L. Tai
DAC
2007
ACM
14 years 8 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...