50 search results - page 5 / 10 » Design Rewiring Using ATPG |
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
CONEXT
2008
ACM
13 years 8 months ago
2008
ACM
A foundational issue underlying many overlay network applications ranging from routing to peer-to-peer file sharing is that of connectivity management, i.e., folding new arrivals ...
VTS
2008
IEEE
14 years 1 months ago
2008
IEEE
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
ASPDAC
1995
ACM
13 years 10 months ago
1995
ACM
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...