870 search results - page 119 / 174 » Design Tradeoffs for SSD Performance |
135
Voted
FPL
2001
Springer
15 years 8 months ago
2001
Springer
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between...
99
Voted
ITC
2000
IEEE
15 years 8 months ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
127
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DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
112
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GECCO
2006
Springer
15 years 7 months ago
2006
Springer
Within the last two decades, Receiver Operating Characteristic (ROC) Curves have become a standard tool for the analysis and comparison of classifiers since they provide a conveni...
126
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DAC
2005
ACM
15 years 6 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...