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DATE
2002
IEEE
154views Hardware» more  DATE 2002»
14 years 18 days ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
SIGMETRICS
2008
ACM
121views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Disk scrubbing versus intra-disk redundancy for high-reliability raid storage systems
Two schemes proposed to cope with unrecoverable or latent media errors and enhance the reliability of RAID systems are examined. The first scheme is the established, widely used d...
Ilias Iliadis, Robert Haas, Xiao-Yu Hu, Evangelos ...
DAC
2006
ACM
14 years 8 months ago
Timing-based delay test for screening small delay defects
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
SOSYM
2010
176views more  SOSYM 2010»
13 years 6 months ago
On challenges of model transformation from UML to Alloy
Abstract The Unified Modeling Language (UML) is the de facto language used in the industry for software specifications. Once an application has been specified, Model Driven Arch...
Kyriakos Anastasakis, Behzad Bordbar, Geri Georg, ...
MICRO
2005
IEEE
117views Hardware» more  MICRO 2005»
14 years 1 months ago
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation
Recent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into...
Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cr...