8 search results - page 1 / 2 » Design and Implementation of Move-Based Heuristics for VLSI ... |
JEA
2000
13 years 7 months ago
2000
DAC
1999
ACM
14 years 8 months ago
1999
ACM
We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling a...
ASPDAC
2000
ACM
13 years 11 months ago
2000
ACM
Multilevel Fiduccia-Mattheyses MLFM hypergraph partitioning 3, 22, 24 is a fundamental optimization in VLSI CAD physical design. The leading implementation, hMetis 23 , has sinc...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
We empirically assess the implications of fixed terminals for hypergraph partitioning heuristics. Our experimental testbed incorporates a leading-edge multilevel hypergraph partit...
GECCO
2003
Springer
14 years 20 days ago
2003
Springer
Abstract. In this paper, we propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local op...