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CHES
1999
Springer
104views Cryptology» more  CHES 1999»
13 years 11 months ago
A Scalable Architecture for Montgomery Multiplication
Abstract. This paper describes the methodology and design of a scalable Montgomery multiplication module. There is no limitation on the maximum number of bits manipulated by the mu...
Alexandre F. Tenca, Çetin Kaya Koç
ICCD
2000
IEEE
137views Hardware» more  ICCD 2000»
13 years 12 months ago
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh...
ISSS
1995
IEEE
117views Hardware» more  ISSS 1995»
13 years 11 months ago
Scheduling and resource binding for low power
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
Enric Musoll, Jordi Cortadella
FPL
2010
Springer
180views Hardware» more  FPL 2010»
13 years 5 months ago
A Karatsuba-Based Montgomery Multiplier
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip L...
HIPEAC
2009
Springer
14 years 2 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali