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» Design and evaluation of an auto-memoization processor
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DAC
2002
ACM
14 years 8 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
FPL
2010
Springer
155views Hardware» more  FPL 2010»
13 years 5 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber
HPCA
1995
IEEE
13 years 11 months ago
The Effects of STEF in Finely Parallel Multithreaded Processors
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
Yamin Li, Wanming Chu
HPCA
1998
IEEE
13 years 12 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
BMCBI
2008
111views more  BMCBI 2008»
13 years 7 months ago
MLIP: using multiple processors to compute the posterior probability of linkage
Background: Localization of complex traits by genetic linkage analysis may involve exploration of a vast multidimensional parameter space. The posterior probability of linkage (PP...
Manika Govil, Alberto Maria Segre, Veronica J. Vie...