In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Abstract. Several types of logic gates suitable for leakage-proof computations have been put forward [1,2,3,4]. This paper describes a method, called “backend duplication” to a...
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu,...
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
This paper will explore the SNet model that Hunter College of the City University of New York developed and implemented. During the Spring of 2002, CUNY as a central organization ...