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» Design and implementation of WIRE Diameter
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ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
14 years 6 months ago
Implementing Caches in a 3D Technology for High Performance Processors
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
Kiran Puttaswamy, Gabriel H. Loh
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
14 years 1 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
LCN
2008
IEEE
14 years 4 months ago
IPclip: An architecture to restore Trust-by-Wire in packet-switched networks
—During the last decades, the Internet has steadily developed into a mass medium. The target group radically changed compared to, e.g., the 90s. Because virtually everyone has ac...
Harald Widiger, Stephan Kubisch, Peter Danielis, J...
PEPM
2009
ACM
15 years 10 months ago
Static Consistency Checking for Verilog Wire Interconnects
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
Cherif Salama, Gregory Malecha, Walid Taha, Jim Gr...
ICCD
1991
IEEE
65views Hardware» more  ICCD 1991»
14 years 1 months ago
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)
This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allow...
Mark E. Dean, David L. Dill, Mark Horowitz