59 search results - page 4 / 12 » Design diagnosis using Boolean satisfiability |
JSAT
2006
13 years 9 months ago
2006
Several propositional fragments have been considered so far as target languages for knowledge compilation and used for improving computational tasks from major AI areas (like infe...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding b...
ITC
2002
IEEE
14 years 2 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...