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» Design issues for dynamic voltage scaling
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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 2 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
DAC
2008
ACM
14 years 8 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
DAC
2009
ACM
14 years 8 months ago
Enabling adaptability through elastic clocks
Power and performance benefits of scaling are lost to worst case margins as uncertainty of device characteristics is increasing. Adaptive techniques can dynamically adjust the mar...
Emre Tuncer, Jordi Cortadella, Luciano Lavagno
DSD
2006
IEEE
120views Hardware» more  DSD 2006»
14 years 1 months ago
Adaptive Power Management for the On-Chip Communication Network
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...
Guang Liang, Axel Jantsch