102 search results - page 3 / 21 » Design of Clock Distribution Networks in Presence of Process... |
DAC
2008
ACM
14 years 9 months ago
2008
ACM
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on m...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
We present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the...
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
ICASSP
2011
IEEE
13 years 7 days ago
2011
IEEE
Recently, the maximum likelihood estimator (MLE) and Cramer-Rao Lower Bound (CRLB) were proposed with the goal of maximizing and assessing the synchronization accuracy in wireless...