195 search results - page 18 / 39 » Design of clocked circuits using UML |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
ITC
1996
IEEE
14 years 3 hour ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...