2945 search results - page 107 / 589 » Designing and Implementing Malicious Hardware |
ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
— In this paper an architecture, signal reconstruction algorithm and first-ever implementation of an asynchronous delta-sigma converter are presented. The signal reconstruction ...
138
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes an...
DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...
148
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MJ
2006
15 years 4 months ago
2006
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
112
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract— In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with ...