2945 search results - page 27 / 589 » Designing and Implementing Malicious Hardware |
118
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ISCAS
2003
IEEE
15 years 9 months ago
2003
IEEE
The goal of the research is twofold First, the derivation of a design methodology for FIR filters implementation based on Residue Number System (RNS), aiming at power, delay and h...
135
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APCCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
127
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DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
106
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract— This paper introduces a novel four-order system, which can generate one-directional (1-D) n−torus, twodirectional (2-D) n × m −torus, three-directional (3-D) n × ...
127
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MSS
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...