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IPPS
2009
IEEE
15 years 10 months ago
CellMR: A framework for supporting mapreduce on asymmetric cell-based clusters
The use of asymmetric multi-core processors with onchip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise...
M. Mustafa Rafique, Benjamin Rose, Ali Raza Butt, ...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
15 years 10 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
138
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ISORC
2009
IEEE
15 years 10 months ago
Embedded JIT Compilation with CACAO on YARI
Java is one of the most popular programming languages for the development of portable workstation and server applications available today. Because of its clean design and typesafe...
Florian Brandner, Tommy Thorn, Martin Schoeberl
MICRO
2009
IEEE
191views Hardware» more  MICRO 2009»
15 years 10 months ago
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
Mainak Chaudhuri
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
15 years 10 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
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