453 search results - page 36 / 91 » Designing hardware with dynamic memory abstraction |
137
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
160
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ISCA
2011
IEEE
14 years 7 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
127
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
150
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
155
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CODES
2005
IEEE
15 years 9 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...