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EURODAC
1995
IEEE
152views VHDL» more  EURODAC 1995»
13 years 11 months ago
Information model of a compound graph representation for system and architecture level design
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
Peter Conradi
DAC
1999
ACM
14 years 1 days ago
Microprocessor Based Testing for Core-Based System on Chip
The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC. The novel feature of the approach is the use an embedde...
Christos A. Papachristou, F. Martin, Mehrdad Noura...
CODES
2008
IEEE
14 years 2 months ago
Extending open core protocol to support system-level cache coherence
Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range...
Konstantinos Aisopos, Chien-Chun Chou, Li-Shiuan P...
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
14 years 1 days ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
14 years 2 months ago
Reducing peak power with a table-driven adaptive processor core
The increasing power dissipation of current processors and processor cores constrains design options, increases packaging and cooling costs, increases power delivery costs, and de...
Vasileios Kontorinis, Amirali Shayan, Dean M. Tull...