Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...
We present a novel non-linear error coding framework which incorporates strong adversarial fault detection capabilities into identity based encryption schemes built using Tate pai...
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
An underlying assumption for N-version programming technique is that independently developed versions would fail in a statistically independent mannel: Howevel; empirical studies ...
Gwang Sik Yoon, Sung Deok Cha, Yong Rae Kwon, Chan...
CMOS scaling increases susceptibility of microprocessors to transient faults. Most current proposals for transient-fault detection use full redundancy to achieve perfect coverage ...