73 search results - page 8 / 15 » Deterministic Logic BIST for Transition Fault Testing |
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
TCAD
2002
13 years 7 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
VLSID
2005
IEEE
14 years 1 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...