This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...