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» Developing a Foundation for Code Optimization
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MICRO
2007
IEEE
133views Hardware» more  MICRO 2007»
14 years 2 months ago
Revisiting the Sequential Programming Model for Multi-Core
Single-threaded programming is already considered a complicated task. The move to multi-threaded programming only increases the complexity and cost involved in software developmen...
Matthew J. Bridges, Neil Vachharajani, Yun Zhang, ...
AUIC
2005
IEEE
14 years 1 months ago
Real-time 3D Finger Pointing for an Augmented Desk
The augmented desk is gaining popularity in recent HCI research. Its layout of a large horizontal screen on the desk enhances immersive and intense collaborative experiences. A re...
Le Song, Masahiro Takatsuka
ICPPW
2005
IEEE
14 years 1 months ago
Speculative Parallel Threading Architecture and Compilation
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
Xiao-Feng Li, Zhao-Hui Du, Chen Yang, Chu-Cheow Li...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 11 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...
CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan