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» Diagonal routing in high performance microprocessor design
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DATE
2006
IEEE
95views Hardware» more  DATE 2006»
14 years 2 months ago
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault d...
Paolo Bernardi, Ernesto Sánchez, Massimilia...
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 2 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
DAC
1998
ACM
14 years 9 months ago
Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce
This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the gr...
Jaewon Oh, Massoud Pedram
CONEXT
2009
ACM
13 years 9 months ago
MDCube: a high performance network structure for modular data center interconnection
Shipping-container-based data centers have been introduced as building blocks for constructing mega-data centers. However, it is a challenge on how to interconnect those container...
Haitao Wu, Guohan Lu, Dan Li, Chuanxiong Guo, Yong...
DATE
1998
IEEE
91views Hardware» more  DATE 1998»
14 years 21 days ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...