35 search results - page 5 / 7 » Die Stacking (3D) Microarchitecture |
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
We fabricated a 3D-integrated multi-chip sensor separate dies [9]. In this paper, we present a 3D integrated and actuator and demonstrated the ability of communication with tempera...
DAC
2012
ACM
11 years 9 months ago
2012
ACM
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...
CF
2008
ACM
13 years 9 months ago
2008
ACM
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...